Veridae Systems is featured on John Cooley's "My Cheesy Must See List for DAC 2011", please see:

http://www.deepchip.com/gadfly/gad060211.html

SAN DIEGO, CA. –– June 6, 2011 –– Veridae Systems and Mentor Graphics today
announced they’ve partnered to support a complete FPGA development flow combining
Mentor Graphic’s Precision® Synthesis FPGA design tools and Veridae’s Certus or
Corus validation and debug solutions. The combination of tools will accelerate the
development, verification and time-to market of single and multi-FPGA based systems.

“We are thrilled to collaborate with Mentor Graphics to integrate Corus and Certus with
the Precision Synthesis tools,” said Jim Derbyshire, Veridae’s chief executive officer.
“The tools seamlessly interface to offer an easy to use and complete FPGA development
flow including simulation, synthesis and on-chip debug. For the first time, design
engineers have access to the critical link from real hardware back to the design.”

SAN DIEGO, CA. –– June 6, 2011 ––Veridae Systems and the Dini Group today
announced they’ve combined Veridae’s Certus FPGA Prototyping Suite with the Dini
Group’s prototyping and I/O hardware to deliver a complete platform for multi-FPGA
prototyping and debug. The solution is fully tested and available now and will be
demonstrated this week at the Design Automation Conference, Veridae booth 3212.

FPGA-based ASIC prototyping is challenging in many regards with the most time and
effort spent in debug. Conventional approaches require long, repeated cycles of
instrumentation, synthesis, followed by FPGA place & route. Certus dramatically
reduces this time by offering a debug platform that encompasses a single, synchronized
view of a complex ASIC design. And Certus effortlessly handles this task across
multiple FPGAs and multiple clock domains. Signal selection and high-speed
troubleshooting is performed without the time intensive cycle of
instrumentation/synthesis/FPGA place & route. As a result, engineers can quickly
pinpoint unexpected behaviors, correct problems, and rapidly move an ASIC prototype
into first mask success.

VANCOUVER, BC –– June 1, 2011 –– Veridae Systems today announced Certus, amulti-FPGA ASIC prototyping validation and debug suite. When paired with a user’schoice of prototyping hardware, partitioning flow, and FPGA CAD tools, Certus provides the key enabling technology of a complete, easy to implement, and best-in-class prototyping solution. Certus has been fully deployed in FPGA prototyping groups of leading companies and is available now.

Verification and validation engineers want to see a complete ASIC design functioning atclose to full speed and with real I/O. Until now, the view of the design has been splintered into the individual FPGA views by available debug tools. Certus solves this challenge by providing a single, fully synchronized view across all of the FPGAs and allof the clock domains, giving users the true ASIC design perspective of the prototype environment for the first time.

EDA Newcomer Veridae Systems lands on Annual What to See at DAC Report From Top Analyst Gary Smith EDA

VANCOUVER, BC.

 May 31, 2011 ––Veridae Systems was named by top EDA analyst Gary Smith among the leading companies to visit at the 48th Annual Design Automation Conference, to be held in San Diego from June 5-10.

Veridae is a newcomer to the EDA market, having launched the Clarus Post Silicon Validation Suite last fall. Since, the company has added the Clarus suite for pre-silicon ASIC FPGA prototyping verification, and the Certus suite for multi-FPGA prototyping. Veridae’s technology has filled a significant gap in available tools for design, validation and prototyping of complex devices. FPGA-based systems and ICs are more complex and operate at faster speeds – a combination that has pushed the

Veridae Systems is pleased to be recognized by Rocket Builders on their annual "Emerging Rockets" list for 2011.  "Emerging Rockets" is a recognition program for British Columbia technology companies that are not yet in a high revenue growth stage but have great potential for investment and market breakthroughs in the coming year.  "We are very pleased to have been recognized for the second year in a row", said Jim Derbyshire, CEO of Veridae Systems, "We have made great strides this year with the formal launch of our Clarus family of products and engagements with many top-tier semiconductor companies".  Click here for the press release and here to go to the Rocket Builders website.

Veridae Systems Simplifies Validation and Debug of Complex FPGA-based Systems with the New Corus Suite

SAN JOSE, CA  May 2, 2011  Veridae Systems today announced the Corus validation and debug software suite for complex FPGA-based systems. The Corus software suite is the first on the market to deliver a synchronized view of multi-FPGA systems both on- and off-chip, across devices and timing domains. With access to any observed signal, any time, designers and validation engineers can quickly pinpoint failures and fix root causes. The enhanced visibility delivered by Corus allows debug problems that previously required weeks, or even months, to be resolved in hours.

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