“Certus is a significant addition to our design flow, and has the potential to greatly accelerate debug,” said Dave Garau, ASIC prototyping and validation manager at Teradici. "The software is easy to use and implement, and outperforms existing solutions by a considerable margin.”

When debugging ASIC prototypes, conventional debug and verification solutions nowrequire long cycles of synthesis, and place and route software run times. Certus enablessignal selection and high-speed trouble shooting without running synthesis and routingfor every change. As a result, engineers can quickly pinpoint and understand unexpectedbehaviors, correct problems, and rapidly move ASIC designs into production.

“Certus was designed by IC designers aiming to solve the challenges associated with prototyping, debug and verification of today’s faster, more integrated FPGA-based systems,” said Jim Derbyshire, Veridae’s chief executive officer. “We are quite pleased with the customer feedback. Early adopters have helped us tune Certus to being an ideal solution for customers seeking best-in-class tools to reduce both prototyping time and ASIC time to market.”

The Certus Suite for FPGA prototyping provides a synchronized view of the entire system, including serial I/O, busses, software code and FPGA hardware. Certus does notrequire custom connectors or I/O resources and can be deployed on all existing platforms. The suite is based on Veridae’s proven set of software tools that includes theImplementor, which helps to design and implement minimized on-chip signal captureprobes quickly and efficiently; the Analyzer, which manages the captured data; and theInvestigator, which relates the information back to the design, interpolates the data anddisplays a larger signal set. The combination of these tools allows designers to have asingle synchronized view for faster FPGA-based system validation and debug withoutendless re-synthesis and place and route.