Speeding Post-Silicon Validation and Debug
Enabling Workarounds
Even with perfect RTL, exhaustive validation is difficult and time consuming. The problem is amplified in SoC (system-on-chip) designs, where hardware, software, and firmware must come together at first silicon. When unexpected behaviors happen, design teams often struggle with limited data to determine the root cause. They frequently spend hours, days, or even weeks, stalling development and missing market windows. Clarus lets you investigate quickly and efficiently so you can get your project back on track.
Saving the time and cost of designing, implementing, testing, and supporting your own solution, Clarus delivers fast validation and debugging of complex systems. The Implementor software makes implementing on-chip capture simple. It allows design teams to quickly generate an optimized on-chip infrastructure that works across multiple clock domains in minutes. And because Clarus works at the RTL level, it integrates seamlessly into any CAD flow.
The Clarus Infrastructure's highly configurable Any-Signal-Anytime architecture delivers real-time visibility into any number of internal signals you wish and makes the best possible use of on-chip resources and knowledge of your design RTL to minimize the area requirement. Using less area than current ad-hoc approaches, Clarus provides significantly greater visibility that can be easily adjusted to suit any die size budget.
Analyzer then lets you validate quickly providing logic analyzer style views and complex trigger conditions that use your RTL level naming. Make use of built-in compression techniques and conditional capture to capture long traces of just the signals you want to see, synchronized to your trigger and aligned across all internal timing domains simultaneously. What's more, you can use the alternate command line interface to automate captures over long periods of time and collect the information you need to understand complex behavior that manifests over long periods of time.
Key to minimizing the area requirement in ASICs is the breakthrough Investigator software. Using knowledge of your RTL and multiple data captures from your IC, Clarus infers a great many more signals, so you can have the most complete picture possible and find the root cause of unexpected behavior quickly.
Software workarounds are often possible where an incorrect operation can be detected. Clarus enables software workarounds by allowing microprocessor access to the Clarus infrastructure. The Clarus infrastructure may detect invalid conditions and raise a processor interrupt. The processor can then analyze signal capture data and take appropriate action, avoiding the need for a re-spin.
