A Family of FPGA based Systems Validation & Debug Suites
Imagine how much faster system validation and debug would be if you were able to see a wide synchronized (time correlated) view of all of your system, not only serial I/O, buses and software code, but inside the FPGAs as well. Tektronix’s Corus suites provide this visibility along with many other features that FPGA based system designers have told us they need to speed their time to market and reduce costs.
Corus enables quick insertion of lightweight probes into FPGA designs giving access to a wide signal range without impacting performance. Furthermore, observed signal selection doesn't require FPGA re-synthesis which, when combined with complex triggering, greatly accelerates root cause analysis and speeds validation. Lastly cross triggering can be extended to interoperate with software debuggers and external test equipment to provide a fully synchronized system view. Corus has been designed to meet the needs of FPGA based system prototyping, validation and debug.
Corus offers:
- Very wide signal range with extensive compression to optimize depth
- Synchronized view, on-chip across multiple clock domains and across FPGAs
- Zoom from system view to clock cycle accurate detailed data
- Any observed signal, any time avoiding frequent FPGA re-synthesis
- Complex triggering and cross triggering with test equipment and software debuggers
- Enables remote debug in the field solutions
- Fast and easy capture probe insertion in FPGAs
Corus Work Flow:
Tektronix’s Corus is a family of suites of software tools and IP providing everything required to enhance visibility on-chip and off-chip. At the design stage, the easy-to-use Implementor tool applies advanced proprietary algorithms to help you design and implement minimized on-chip signal capture probes quickly and efficiently on your FPGAs. During validation, the capture probes are managed by an Analyzer tool through the JTAG port or microprocessor interface and complex and cross triggers are easily set up. Corus’ every observed signal, any time, feature avoids seemingly endless re-synthesis when selecting signals. The resulting highly compressed captures are processed off-chip by proprietary algorithms that recreate the internal chip data and resynchronize the captures from different clock domains and FPGAs into one view.
Corus lets you see what's inside the FPGAs offering both on and off chip capture to provide the optimum visibility for faster system validation and debug. Its embedded capture offers the widest signal range with compression to optimize depth within available memory.