As ASICs and SoCs push into 45nm and 22nm process technologies, ASIC prototyping on FPGAs, or simply FPGA prototyping, has become a key enabler for functional verification of complex designs.  Offering speeds up to 300MHz dependent on partitioning, FPGA prototyping offers a low-cost way of verifying your RTL under real stimulus and developing the complex software that now comprises 50% of development efforts.

Acceleration and emulation system vendors claim that running a testbench and frequent RTL iterations is sufficient to understand complex IC behavior, but the performance of these systems is often far too slow for bugs that only manifest over time under a complex set of hardware, software, and stimulus conditions.  Add to that the cost and complexity of designing a full-chip testbench, it’s easy to see why 60% of ASIC design teams now use FPGA prototyping as part of their verification process.

Visibility into FPGA designs has challenged designers, hampered by inadequate tools that offer access to only a limited number of signals, do not support multiple clock domains or multiple FPGAs, and make poor use of FPGA resources.  Tektronix EIG’s breakthrough debug architectures and proprietary software algorithms solve these problems with an easy-to-use system that allows engineers to quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly verify complex ASIC designs before tape-out. Tektronix EIG lets you see what's inside.