Higher levels of integration, integrated high-speed I/O, and embedded systems have made great advances with respect to the functionality and unit cost of modern integrated circuits (ICs).  However, these factors have also conspired to stretch schedules and increase development cost: in many cases, more than half of a complex IC's development cost is now incurred after initial prototypes arrive.  Despite the industry's best efforts to increase verification coverage through emulators, the expanding state-space of modern ASIC (application specific integrated circuit) designs has kept verification certainty an elusive goal.  It's no surprise, then, that fewer than 40% of ASICs achieve first pass success.

Even with perfect RTL, exhaustive validation is tedious and time consuming.  The problem is amplified in SoC (system-on-chip) designs, where hardware, software, and firmware must come together at first silicon.  When unexpected behavior happens, design teams may spend hours, days, or even weeks to determine the root cause, stalling development and missing market windows.  Without the full visibility offered by simulation, validation engineers are constrained by the information available: pins and registers.  

The key to understanding complex device behavior and hardware/software interaction is internal visibility.  Capturing state machine data in internal registers or routing signals of interest to external pins is common if not ubiquitous, and recently emulation platforms have helped designer's efforts to reduce the number of bugs that make it into first silicon.  These ad-hoc approaches add value, but do not scale to meet the demands of today's complex ICs and SoCs.  

Tektronix EIG's products allow engineers to quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move devices into production.  Our novel combination of hardware IP and proprietary software algorithms take the guesswork out of post-silicon debug.  Tektronix EIG lets you see what's inside.