System Validation

In the past, low to medium volume system products were built of multiple standard parts with “glue logic” in simple FPGAs. More and more these systems have grown to offer higher custom functionality and integration by using increasingly complex FPGAs. As a result the interconnect buses, embedded processors, interblock I/O and clocks are no longer accessible, they are often buried deep inside the FPGAs. In addition, the I/O of the FPGAs within the system is very limited compared to the number of signals required, and high speed serial connections are increasing used. The result is that the traditional validation techniques purely using logic analyzers have broken down.

The FPGA vendors responded with FPGA focused simple tools to facilitate routing signals off FPGA in various ways. They have offered routing of a small number signals off-chip, limited by the I/O available, to a logic analyzer. In addition, there have been solutions to embed on-chip capture circuits of a pre-determined small number of signals that require re-synthesis to change the signals available for capture. There are also some EDA tools which offer similar features in an easier to use format.

Tektronix EIG believes the recent and future generations of complex FPGAs have changed the validation requirements in another major step. No longer will single clock domain, limited signal views inside a single FPGA be sufficient. There is a need to accelerate the process of proving correct operation and finding root causes during debug by greatly increasing visibility and providing a systematic approach to deal with the greater complexity. We believe system validation teams need easy to use and quick to learn tools that give them a synchronized view: inside FPGAs, across clock domains, across multiple FPGAs, aligned with external test equipment and software debuggers.